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Prados, C.

Paper Title Page
THPL011 FEC in Deterministic Control Systems over Gigabit Ethernet 147
 
  • C. Prados, T. Fleck
    GSI, Darmstadt
  
  Forward Error Correction (FEC) is a technique for recovering from bit errors and packet losses in real-time network applications. Classic recovering strategies, like TCP retransmission, are not suitable due to delay, timing and bandwidth constraints. In this paper, the authors introduce the FEC techniques in a novel deterministic fieldbus, White Rabbit* (WR), developed over frame-based computer networking technology, Gigabit Ethernet. WR provides an effective and resilient way to serve as a deterministic data transfer medium and to interconnect large distributed systems, like Control Systems for Particles Accelerators. The reliability of WR falls on the FEC, which provides the means to guarantee that only one “control message” per year will be lost or irretrievable as a result of the Bit Error Rate of the physical medium (fiber optic or copper). The FEC code proposed by the authors is a VHDL hardware design, based on LDPC** and Fountain codes***, and tailored for broadcast/unicast communication in switched networks over noisy channels without retransmission.

* "The White Rabbit" Project, ICALEPCS 2009
** A mathematical theory of communication" C. E. Shannon
*** Fountain Codes, David J. C. MacKay

 
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FRCOMA01 ‘WhiteRabbit’ - A novel, high precision timing system 192
 
  • M. Kreider, R. Baer, T. Fleck, C. Prados
    GSI, Darmstadt
  • E. G. Cota, J. Serrano, T. Wlostowski
    CERN, Geneva
  
  The WhiteRabbit timing network is a deterministic field bus, based on synchronous GBit Ethernet and the Precision Timing Protocol (PTP). The WR protocol was designed to provide precise timing and event distribution for high end real-time systems and was therefore chosen as the timing basis for the new GSI FAIR accelerator facility. With precise phase measurement to compensate for signal propagation delay, a timing accuracy down to sub-nanosecond range is feasible. To achieve necessary determinism and robustness (packet loss of ~10-12 ), an OSI layer two forward error correction and QOS protocol have been introduced. Special switches wield the WR protocol, while being transparent to normal Ethernet traffic. Switch hardware is currently under development at CERN and will be a mixed FPGA/CPU solution. Working prototype cards have been introduced at the 3rd WR Workshop at CERN in 2009, demonstrating phase measurement and PTP capabilities. The presentation will contain detail on technical concepts, current project status, as well as future areas of application will be part of the discussion.  
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