Kreider, M.

Paper	Title	Page
WEPL011	FAIR Timing Master	50
	M. Kreider, T. Fleck GSI, Darmstadt
	In the scope of building the new FAIR facility, GSI will change its timing system to Whiterabbit. The FAIR system will resemble a tree topology, with a single master unit on top, followed by several layers of WR switches, down to about two thousand timing receivers throughout the facility. The Timing Master will be a mixed FPGA/CPU solution, which translates physical requirements into timing events and feeds them into the WR network. Macros in the FPGA resemble a 32x multicore with a strongly reduced instruction-set, each event processor responsible for a specific part of the facility. These processors interact in realtime, reacting to interlocks and conditions and ensuring determinism by parallel processing. A powerful CPU prepares the timing event tables and provides an interface to the controls system. These tables are loaded into the RAMs of each participating processor, controlling their behaviour and event output. GSI is currently working on the WR timing system in close collaboration with CERN, making this system the future of GSI/FAIR. The poster will cover technical details on the expected timing scenario, macro internals and discussion on possible future development.
	Poster
FRCOMA01	‘WhiteRabbit’ - A novel, high precision timing system	192
	M. Kreider, R. Baer, T. Fleck, C. Prados GSI, Darmstadt E. G. Cota, J. Serrano, T. Wlostowski CERN, Geneva
	The WhiteRabbit timing network is a deterministic field bus, based on synchronous GBit Ethernet and the Precision Timing Protocol (PTP). The WR protocol was designed to provide precise timing and event distribution for high end real-time systems and was therefore chosen as the timing basis for the new GSI FAIR accelerator facility. With precise phase measurement to compensate for signal propagation delay, a timing accuracy down to sub-nanosecond range is feasible. To achieve necessary determinism and robustness (packet loss of ~10-12 ), an OSI layer two forward error correction and QOS protocol have been introduced. Special switches wield the WR protocol, while being transparent to normal Ethernet traffic. Switch hardware is currently under development at CERN and will be a mixed FPGA/CPU solution. Working prototype cards have been introduced at the 3rd WR Workshop at CERN in 2009, demonstrating phase measurement and PTP capabilities. The presentation will contain detail on technical concepts, current project status, as well as future areas of application will be part of the discussion.
	Slides