<xml>
  <records>
    <record>
       <contributors>
          <authors>
             <author>Ma, H.</author>
             <author>Doolittle, L.R.</author>
             <author>Nassiri, A.</author>
             <author>Ratti, A.</author>
             <author>Smith, T.L.</author>
             <author>Sun, Y.</author>
          </authors>
       </contributors>
       <titles>
          <title>
             An Internet Rack Monitor-Controller for APS LINAC RF Electronics Upgrade
          </title>
       </titles>
		 <publisher>JACoW</publisher>
       <pub-location>Geneva, Switzerland</pub-location>
		 <isbn>978-3-95450-180-9</isbn>
		 <electronic-resource-num>10.18429/JACoW-NAPAC2016-TUPOA14</electronic-resource-num>
		 <language>English</language>
		 <pages>314-316</pages>
       <pages>TUPOA14</pages>
       <keywords>
          <keyword>ion</keyword>
          <keyword>controls</keyword>
          <keyword>linac</keyword>
          <keyword>network</keyword>
          <keyword>klystron</keyword>
       </keywords>
       <work-type>Contribution to a conference proceedings</work-type>
       <dates>
          <year>2017</year>
          <pub-dates>
             <date>2017-01</date>
          </pub-dates>
       </dates>
       <urls>
          <related-urls>
              <url>http://dx.doi.org/10.18429/JACoW-NAPAC2016-TUPOA14</url>
              <url>https://jacow.org/napac2016/papers/tupoa14.pdf</url>
          </related-urls>
       </urls>
       <abstract>
          To support the current research and development in APS LINAC area, the existing LINAC rf control performance needs to be much improved, and thus an upgrade of the legacy LINAC rf electronics becomes necessary. The proposed upgrade plan centers on the concept of using a modern, network-attached, rack-mount digital electronics platform 'Internet Rack Monitor-Controller (or IRMC) to replace the existing analog ones on the legacy crate/backplane-based hardware. The system model of the envisioned IRMC is basically a 3-tier stack with a high-performance processor in the mid- layer to handle the general digital signal processing (DSP). The custom FPGA IP's in the bottom layer handle the high-speed, real-time, low-latency DSP tasks, and provide the interface ports. A network communication gateway, in conjunction with an embedded event receiver (EVR), in the top layer merges the Internet Rack Monitor-Controller device into the networks of the accelerator controls infrastructure. Although the concept is very much in trend with today's Internet-of-Things (IoT), this implementation has actually been used in accelerators for over two decades.
       </abstract>
    </record>
  </records>
</xml>
