The novel Coupling-Loss-Induced-Quench (CLIQ) concept will be part of the quench protection system of the High Luminosity Large Hadron Collider (HL-LHC) Inner Triplet superconducting magnets at CERN. Several units of two distinct CLIQ prototype variants were produced to validate the CLIQ novel protection concept and define the system parameters for the required performance. Subsequently, these units were further enhanced by introducing additional redundancy, advanced monitoring systems, and improved safety features. These improvements culminated in the development of the third and final version. This paper provides insights into the evolution from prototypes to the final version to be installed in the machine, shedding light on the outcomes of comprehensive safety and electromagnetic compatibility (EMC) tests, coupled with extensive operational assessments.

The Quench Heater Discharge Power Supplies (HDS) are magnet protection devices installed in the Large Hadron Collider (LHC) that, upon detection of a magnet quench, release energy into the copper-plated stainless-steel strip heaters, inducing a resistive transition all along the superconducting coils. Such a distributed internal heating ensures an even energy dissipation across the entire volume, preventing local overheating and magnet damage. Over 6000 HDS units have been operational in the LHC tunnel since 2007. The new HDS design for protection of the High Luminosity LHC (HL-LHC) Inner Triplet magnets, to be installed in the Long Shutdown starting in 2026, calls for a more advanced design with up-to-date components resulting in a higher reliability of the HDS units. Several HDS prototypes were produced at CERN, eventually culminating in the development of the HL-LHC HDS version to be installed in the accelerator. This paper describes the design of the upgraded HDS units and the comprehensive safety and electromagnetic compatibility (EMC) tests, coupled with extensive operational tests, including irradiation tests, that have been conducted.

The Beam Interlock System (BIS) is the backbone of the machine protection system throughout the accelerator complex at CERN, from LINAC4 to the LHC. After 15 years of flawless operation, a new version of the BIS is currently being produced and will be installed in the LHC, SPS and North Area during CERN’s Long Shutdown 3, planned to start in 2026. Overall, more than 3,000 Printed Circuit Boards will be produced and assembled outside CERN. In addition, more than 120,000 lines of firmware and supporting scripts are written to implement the critical and monitoring functionalities of the BIS. Both hardware and firmware need to be thoroughly tested before installation and operation to guarantee the high levels of reliability and availability required by the operation of the accelerators. In this paper we present the testing methodology including the development of dedicated testbeds for hardware validation, the use of comprehensive simulation and continuous integration for firmware development, and the implementation of automated tests for system-level functional validation.

The Safe Machine Parameter (SMP) system is an electronic hardware-based system which has been an integral part of the LHC’s machine protection strategy since it started operation. Its primary objective is to provide several parameters and interlock signals to critical machine protection users across the LHC and SPS accelerators, whilst prioritizing high reliability and availability. After almost two decades of operation, there is a need to upgrade the SMP hardware electronics. In the High Luminosity LHC era the requirements of connected systems have changed, leading to new system functions and operational requirements which must be integrated into the new design. This paper details the electronic design considerations of developing the second-generation SMP. The general distribution of parameters relies on the CERN WhiteRabbit timing network renovation, for which dedicated high-precision clock components were selected and tested on a prototype board. Details of the hardware design and validation are discussed, along with the comprehensive upgrades aimed at delivering an SMP system with expanded monitoring and diagnostic features.