| Title |
Upgrade of Digital BPM Processor at DCLS and SXFEL |
| Authors |
- L.W. Lai, F.Z. Chen, Y.B. Lengpresenter, T. Wu, Y.B. Yan
SSRF, Shanghai, People's Republic of China
- J. Chen
SINAP, Shanghai, People's Republic of China
|
| Abstract |
A digital BPM processor has been developed at 2016 in SINAP for DCLS and SXFEL, which are FEL facilities built in China. The stripline BPM and cavity BPM processors share the same hardware platform and firmware, but the processing algorithms implemented in EPICS IOC on the ARM CPU are different. The capability of the ARM limits the processing speed to 10 bunches per second. Now the bunch rate of DCLS and SXFEL are going to increase from 10Hz to 50Hz. To meet the higher processing speed requirements, the processor firmware and software are upgraded in 2017. All BPM signal processing algorithms are implemented in FPGA, and EPICS IOC reads results only. After the upgrade, the processing speed reach 120 bunches per second. And this is also a good preparation for future Shanghai Hard-X ray FEL, which bunch rate is about 1MHz.
|
| Paper |
download THPML071.PDF [1.488 MB / 4 pages] |
| Export |
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| Conference |
IPAC2018, Vancouver, BC, Canada |
| Series |
International Particle Accelerator Conference (9th) |
| Proceedings |
Link to full IPAC2018 Proccedings |
| Session |
MC3/6/7 Poster Session |
| Date |
03-May-18 16:00–17:30 |
| Main Classification |
06 Beam Instrumentation, Controls, Feedback, and Operational Aspects |
| Sub Classification |
T03 Beam Diagnostics and Instrumentation |
| Keywords |
FEL, cavity, software, EPICS, FPGA |
| Publisher |
JACoW Publishing, Geneva, Switzerland |
| Editors |
Shane Koscielniak (TRIUMF, Vancouver, BC, Canada); Todd Satogata (JLab, Newport News, VA, USA); Volker RW Schaa (GSI, Darmstadt, Germany); Jana Thomson (TRIUMF, Vancouver, BC, Canada) |
| ISBN |
978-3-95450-184-7 |
| Published |
June 2018 |
| Copyright |
|
