| Title |
Design and Performance of Digital BPM Processor for DCLS and SXFEL |
| Authors |
- L.W. Lai, F.Z. Chen, Y.B. Leng, Y.B. Yan, N. Zhangpresenter
SSRF, Shanghai, People's Republic of China
- J. Chen
SINAP, Shanghai, People's Republic of China
|
| Abstract |
A digital BPM processor has been developed in SINAP, which can be used on the signal processing of both stripline BPM and cavity BPM. The processor is a standalone system and providing 4 channels 120MS/s, 16 bits ADC and powerful Virtex-5 FPGA. The processor has been mas applied on Dalian Coherent Light Source and Shanghai X-ray FE. The processor specification and performance evaluations including lab and beam tests will be introduced.
|
| Funding |
Work supported by National Natural Science Foundation (No. 11305253, 11575282) |
| Paper |
download MOPAB092.PDF [0.651 MB / 3 pages] |
| Export |
download ※ BibTeX
※ LaTeX
※ Text/Word
※ RIS
※ EndNote |
| Conference |
IPAC2017, Copenhagen, Denmark |
| Series |
International Particle Accelerator Conference (8th) |
| Proceedings |
Link to full IPAC2017 Proccedings |
| Session |
Posters Monday 1 |
| Date |
15-May-17 16:00–18:00 |
| Main Classification |
06 Beam Instrumentation, Controls, Feedback and Operational Aspects |
| Sub Classification |
T03 Beam Diagnostics and Instrumentation |
| Keywords |
FPGA, pick-up, cavity, controls, electronics |
| Publisher |
JACoW, Geneva, Switzerland |
| Editors |
Volker RW Schaa (GSI, Darmstadt, Germany); Gianluigi Arduini (CERN, Geneva, Switzerland); Juliana Pranke (ESS, Lund, Sweden); Mike Seidel (PSI, Villigen, Switzerland); Mats Lindroos (ESS, Lund, Sweden) |
| ISBN |
978-3-95450-182-3 |
| Published |
May 2017 |
| Copyright |
|
