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DOI:10.18429/JACoW-IPAC2016-WEPOR044
Title Fpga Implementation of a Control System for the LANSCE Accelerator
Authors
  • S. Kwon, L.J. Castellano, D.J. Knapp, J.T.M. Lyles, M.S. Prokop, D. Rees, A. Scheinker, P.A. Torrez
    LANL, Los Alamos, New Mexico, USA
Abstract As part of the modernization of the Los Alamos Neutron Science Center (LANSCE), a digital low level RF (LLRF) system was designed. The LLRF control system was implemented in a Field Programmable Gate Array (FPGA) using embedded Experimental Physics and Industrial Control System (EPICS) Input Output Controller (IOC) under the Real-Time Executive for Multiprocessor Systems (RTEMS). Proportional-Integral (PI) feedback controller, static beam feedforward controller, and iterative learning controller are implemented on the FPGA. The closed loop system performance was tested with a 10mA peak current proton beam.
Paper download WEPOR044.PDF [0.974 MB / 3 pages]
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Conference IPAC2016, Busan, Korea
Series International Particle Accelerator Conference (7th)
Proceedings Link to full IPAC2016 Proccedings
Session Poster Session
Date 11-May-16   16:00–18:00
Main Classification 06 Beam Instrumentation, Controls, Feedback and Operational Aspects
Sub Classification T27 Low Level RF
Keywords controls, feedback, cavity, LLRF, FPGA
Publisher JACoW, Geneva, Switzerland
Editors Christine Petit-Jean-Genaz (CERN, Geneva, Switzerland); Dong Eon Kim (PAL, Pohang, Republic of Korea); Kyung Sook Kim (PAL, Pohang, Republic of Korea); In Soo Ko (POSTECH, Pohang, Republic of Korea); Volker RW Schaa (GSI, Darmstadt, Germany)
ISBN 978-3-95450-147-2
Published June 2016
Copyright
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cc Creative Commons Attribution 3.0