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URLhttps://doi.org/10.18429/JACoW-ICALEPCS2025-THBG002
TitleFELIX, the ATLAS readout system: from LHC Run 3 to Run 4
Authors
  • R. Luz
    Argonne National Laboratory
AbstractAfter being successfully deployed to read out a subset of the ATLAS detectors during LHC Run 3 (2022-2026), FELIX will serve all ATLAS detectors in LHC Run 4 (2030-2033). FELIX is a router between custom serial links from front-end ASICs and FPGAs to data collection and processing components via a commodity switched network. FELIX is also capable of fixed-latency forwarding the LHC clock, trigger accepts, and resets received from the TTC (Timing, Trigger and Control) system to front-end electronics. FELIX uses FPGA-based PCIe I/O cards installed in commodity servers. To cope with the increased data rate expected after the major upgrade to the LHC and the detector in between runs, the FLX712 Run 3 PCIe Gen3x16 card, based on an AMD Kintex Ultrascale XCKU115 FPGA, will be replaced with the FLX155, a bifurcated 2x PCIe Gen5x8 card equipped with an AMD Versal Premium VP1552 FPGA/SoC. Firmware installed on the FPGA and software running on the FELIX server are also being upgraded to handle the increased data rate.
Paperdownload: THBG002.pdf
CiteBibTeX, LaTeX, Text/Word, RIS, EndNote
Conference20th Int. Conf. Accel. Large Exp. Phys. Control Syst. (ICALEPCS'25)
Series
LocationChicago, IL, USA
Date20-26 Sep 2025
PublisherJACoW Publishing, Geneva, Switzerland
Editorial BoardKent Wootton (ANL), Jeffery Biss (FNAL), Gustavo Bruno (ANL), Jeff Kirchman (ANL), Kelly Jaje (ANL), Denise Skiadopoulos (ANL), SuYin Grass Wang (ANL)
Online ISBN978-3-95450-255-4
Online ISSN2226-0358
Received04 September 2025
Revised24 September 2025
Accepted27 October 2025
Issued25 November 2025
DOI10.18429/JACoW-ICALEPCS2025-THBG002
Pages1346-1350