A new FPGA-based Global Trigger system is intended for the Phase-II Upgrade of the ATLAS experiment at the High-Luminosity Large Hadron Collider (HL-LHC). The system will process data from the experiment with fixed latency to allow the selection of individual collisions of proton bunches with physical potential. Intermediate data from the Global Trigger system are read out for the collisions of interest for trigger decision verification with commodity computing. The readout of the Global Trigger is handled by the readout firmware, which interfaces with the ATLAS readout system. The firmware receives trigger decisions, timing and control signals via the 9.6 Gb/s ATLAS Local Trigger Interface (LTI) link and outputs data via the 25 Gb/s Interlaken link. A prototype of this readout firmware has been designed and tested on the Global Common Module (GCM) boards equipped with AMD Versal Premium FPGAs.

Ten years ago, the PandABox platform was first introduced in Melbourne during the MOCRAF workshop. Originally developed through a collaboration between Synchrotron SOLEIL and Diamond Light Source, PandABox was designed to support multi-technique scanning and feedback applications. Since then, the platform has been widely adopted across synchrotron facilities worldwide—including SOLEIL, DIAMOND, MAX IV, and DESY in Europe; NSLS-II in the United States; HEPS in Asia; and SESAME in Middle-East. With the fourth-generation light sources, there is an increasing need for high-performance, multi-channel encoder processing to enable synchronized data acquisition and motion control during continuous scanning experiments—now a critical feature for automation. In response to these evolving demands, and following discussions within the LEAPS-INNOV WP5.3 project, the opportunity to jointly develop a new state-of-the-art equipment became evident. This effort has since expanded into a broader collaboration that now includes MAX IV, ALBA, and DESY alongside the original partners. This paper presents the new generation of the PandABox platform, offering a comprehensive overview of its integration within EPICS and TANGO control systems. It also outlines future functionalities and the framework of the ongoing international collaboration driving its development.

As the world’s most energetic laser, the National Ignition Facility (NIF) plays a critical role in advancing high energy density physics and inertial confinement fusion research. The NIF relies on a distributed control system to automate setup and execution of experiments. This includes over 1,000 embedded controllers split between 17 distinct types. Most of these controllers were designed in the late 1990s to early 2000s, using platforms ranging from Lontalk microcontrollers to STD Bus single board computers. Over the decades, many of our chosen software technologies, hardware components, and platforms have reached end of life. Therefore, we have begun a modernization effort for the NIF embedded controllers. Modern hardware/software will allow us to procure additional units in order to maintain adequate spares and support upcoming upgrades to the NIF. It will also allow us to tackle incompatibilities developing between our existing firmware and modern IT infrastructures. This paper will provide an overview of our embedded controller strategy. It will focus on component selection, minimizing risk during the transition using an automated test bench, and firmware/hardware upgrades to minimize on-going maintenance costs.

The Distributed I/O Tier (DI/OT) project was initially launched to develop a common, modular hardware platform for custom electronics at the lowest layer of the CERN control system. With the adoption of the AMD Zynq UltraScale+ MPSoC for the high-performance System Board, DI/OT has also become a reference platform for integrating System-on-Chip (SoC) technology into CERN’s control system. This paper presents two key aspects of DI/OT’s role as a SoC reference platform: (1) tools and methodologies to streamline end-application development and (2) integration of DI/OT into CERN’s control system as a Front-End platform. The first aspect includes a user-friendly build system and reference design that enable seamless integration of custom FPGA IP cores and Linux device tree entries while providing the reference design with essential DI/OT functionality and monitoring interfaces for local crate peripherals. This build system also automates synthesis and low-level software compilation to generate a complete bootable binary. The second aspect covers a fail-safe and reliable SoC boot mechanism, network booting of FECOS (a Debian-based CERN Linux image for Front-End Computers), and integration with standard monitoring services. Keywords: System-On-Chip, DI/OT, integration, build-system, fail-safe, monitoring

The low-level RF (LLRF) systems for linear accelerating structures are typically based on heterodyne architectures. The linear accelerators normally have many RF stations and multiple RF inputs and outputs for each station, so the complexity and size of the LLRF system grows rapidly when scaling up. To meet the design goals of being compact and affordable for future accelerators, or upgrade of existing ones, we have developed and characterized the next generation LLRF (NG-LLRF) platform based on the RF system-on-chip (RFSoC) for S-band and C-band accelerating structures. The integrated RF data converters in RFSoC sample and generate the RF signals directly without any analogue mixing circuits, which significantly simplified the architecture compared with the conventional LLRF systems. We have performed high-power tests for the NG-LLRF with the S-band accelerating structure in the Next Linear Collider Test Accelerator (NLCTA) test facility at SLAC National Accelerator Laboratory and a C-band structure prototyped for Cool Cooper Collider (CCC). The NG-LLRF platform demonstrated pulse-to-pulse fluctuation levels considerably better than the requirements of the targeted applications and high precision and flexibility in generating and measuring the RF pulses. In this paper, the characterization results of the platform with different system architectures will be summarized and a selection of high-power test results of the NG-LLRF will be presented and analyzed.

A 4th-generation synchrotron light source demands high-performance mechatronic systems to meet stringent requirements for optical focusing, energy filtering, beam stability, sample positioning, and scanning. SIRIUS*, the facility the Brazilian Synchrotron Light Laboratory (LNLS), has achieved exceptional beam quality, supporting advanced scientific experiments through the continuous development of state-of-the-art mechatronic systems** at its beamlines. A flexible, scalable, and high-performance FPGA-based real-time control architecture has been developed to meet the demanding requirements. It is capable of handling high-dynamic systems with control bandwidth on the order of hundreds of hertz, as well as stable motions at the sub-nanometer scale. This work focuses on the embedded code architecture and implementation, reviewing the hardware topology and its seamless integration enabling the full mechanical capabilities. The design principles, implementation strategies, and performance evaluations demonstrate its effectiveness and potential applicability to advanced control applications. The scalable design has also led to significant improvements in beamline development and deployment throughput, enabling harmonious integration and customization towards a reliable system.

The EIC Common Platform is a modular system architecture which will serve as the basis for the EIC Controls Systems. It consists of a SoC based carrier board with up to two independent pluggable FPGA based Daughtercards. Different types of Daughtercards have custom electronics catering to the specific needs of an application. All types of Daughtercards will have FPGA logic to support a common protocol for communication with the carrier board as well as a basic set of features for programming and telemetry. Logic to support Daughtercard specific functionality will be implemented in the same FPGA. Daughtercard FPGA projects will be organized with a common modular structure to facilitate reuse of IP cores while allowing for flexibility within the Daughtercard specific logic design. The FPGA Firmware Framework (FWK) developed at DESY will be leveraged for managing the generation and building of FPGA projects. The basic functionality and organizational structure of EIC Common Platform Daughtercard FPGA projects is presented.

A challenge that industrial particle accelerators face is the high amounts of noise in sensor readings. This noise obscures essential beam diagnostic and operational data, limiting the amount of information that is relayed to machine operators and beam instrumentation engineers. Machine learning-based techniques have shown great promise in isolating noise patterns while preserving high-fidelity signals, enabling more accurate diagnostics and performance tuning. Our work focuses on the implementation of a real-time FPGA-based noise reduction autoencoder, tested on a Xilinx ZCU104 evaluation kit with the intention of being deployed on industrial particle accelerators in the near future.

The NSLS-II upgrade program investigates the imple-mentation of complex bend magnets based on permanent magnet quadrupoles (PMQs) to achieve ultra-low emit-tance and enhanced brightness. While PMQs provide high field gradients and compact lattice configurations, they also introduce challenges in tunability, thermal stability, radiation resistance, and field quality control. This paper presents progress on the design and assembly of Halbach-style magnets constructed from 16 permanent magnet (PM) wedges. The control system is designed to achieve precise magnetic field quality through a nonlinear multi-input multi-output (MIMO) optimization framework. To address this nonlinear MIMO challenge, machine learning approaches are proposed to support assembly objectives. To enable ML inference, edge AI hardware platforms are evaluated and selected based on the specific requirements of the control system.

Abstract The Los Alamos Neutron Science Center (LANSCE ) has completed a significant modernization effort, migrating from the legacy RICE control system to an entirely EPICS-based infrastructure. A key enabler of this transition has been the development and deployment of modular, object-oriented Industrial I/O (IIO) architectures on National Instruments (NI) cRIO platforms. The Industrial I/O framework provides a reusable and scalable system for controlling and monitoring sensors and instruments. It is built around precompiled FPGA bitfiles accessed through NI’s C application programming interface. Where necessary, LabVIEW real-time code integrates seamlessly with EPICS IOCs. This architecture enables clear separation between control logic and hardware interfaces, supports future maintenance with minimal overhead, and accommodates both modern Linux RT cRIO and legacy VxWorks systems. The result is a flexible and resilient method for managing and improving complex control architectures across LANSCE. This contribution outlines how IIO enables hardware reuse by treating NI cards as modular components with shared logic, abstracting low-level FPGA interaction, and standardizing configurations through parameterized bitfiles and EPICs startup files. The poster and discussion focus on how this approach supports object-like behavior to improve maintainability, scalability, and cross-platform deployments of EPICS-compatible systems. LA-UR-25-24051

Brookhaven National Laboratory (BNL) is currently developing new hardware description language (HDL) code and embedded software for the Electron-Ion Collider (EIC) control system. Part of this effort is modernizing the development process itself, leveraging methodologies and tools that were initially targeted at the software world. These methods include effective source control and project management, modularization and rapid deployment of updated code, automated testing, and in many cases automated code generation. HDL designers additionally face unique challenges compared to software designers, particularly with vendor locking and dependency on particular tools and IP. The FPGA Firmware Framework (FWK), developed by DESY, is a set of tools that helps to both apply these modern methods and to overcome some of those unique challenges. This paper will cover the workflow, successes, and challenges faced when using the FWK. In particular, we will focus on the experience using this workflow to develop a customizable delay generator IP targeting a Zynq FPGA.

A proton pulse charge calculation algorithm in the Beam Power Limiting System (BPLS) at the Spallation Neutron Source (SNS) was developed and implemented in an FPGA. The algorithm calculates one-minute running average of the pulse charges and issues a fault to the Personal Protection System (PPS) and the Machine Protection System (MPS) when a limit is reached. A bit-accurate model of the algorithm was first developed and tested in Matlab® and then implemented and simulated in VHDL using Vivado® design environment. Finally, the algorithm was verified on a µTCA-based hardware platform.

The Advanced Photon Source (APS) recently completed a significant upgrade to its storage ring, replacing all existing components with new ones. One of the newly introduced systems is the waveform monitoring system. This system is a 2U rackmount chassis with 8 ADC inputs, MRF event link and 16 channels of TTL I/O. This is an FPGA-based 8-channel 4 GS/s digitizer that monitors the decoherence and injection high voltage pulser waveforms. The main function of this system is to qualify each pulse and make a decision on whether to proceed with injection or not. This paper presents in detail the development and features of this system.

The Complex Bend (CB) is a novel lattice concept proposed for the NSLS-II upgrade, utilizing permanent magnets instead of traditional electromagnets. This innovative design aims to reduce horizontal emittance from 700 pm to 40 pm and increase beam energy from 3 GeV to 4 GeV, significantly enhancing beam brightness. However, as a new lattice architecture, the CB introduces substantial technical challenges in design, assembly, and verification, particularly in meeting stringent magnetic field requirements. Unlike electromagnets, permanent magnets cannot be adjusted after assembly, making precise design and fabrication critical. These challenges are further compounded by the nonlinear behavior of magnetic fields with respect to magnet position and geometry. To address these issues, we propose integrating advanced FPGA-based hardware with EPICS-based software into a comprehensive control and tuning system. Real-time sensor data, including position, pressure, magnetic field strength, and temperature will be continuously collected and analysed. In addition, AI/ML algorithms will support optimizing magnet positioning and alignment to meet the required field specifications for each CB unit. This presentation will cover the CB mechanical assembly system, electrical hardware design, low-level control software design, and high-level tuning software implementation.

A new general-purpose analog signal digitizer has been designed and prototyped to serve as an upgrade to the legacy Multiplexed Analog to Digital Converter (MADC) system currently in use around the RHIC accelerator and injector complex at BNL. The new system is a standalone rackmount chassis with an embedded System on a Chip (SoC). This is a departure from the traditional VME form factor used by most legacy controls equipment within the Collider Accelerator Department. New features include completely independent channels, real time digital signal processing, large sample buffers, built-in timing links, and high bandwidth network connectivity. Support is included for the legacy timing links as well as future compatibility with the EIC Timing Data Link. The core features, system architecture, and scheme for integration with the controls system network is presented.

Brookhaven National Laboratory (BNL) is currently developing new hardware description language (HDL) code and embedded software for the Electron-Ion Collider (EIC) control system. Part of this effort is modernizing the development process itself, leveraging methodologies and tools that were initially targeted at the software world. These methods include effective source control and project management, modularization and rapid deployment of updated code, automated testing, and in many cases automated code generation. HDL designers additionally face unique challenges compared to software designers, particularly with vendor locking and dependency on particular tools and IP. The FPGA Firmware Framework (FWK), developed by DESY, is a set of tools that helps to both apply these modern methods and to overcome some of those unique challenges. This paper will cover the workflow, successes, and challenges faced when using the FWK. In particular, we will focus on the experience using this workflow to develop a customizable delay generator IP targeting a Zynq FPGA.

WREN is a versatile White Rabbit (WR) node developed for CERN's event-based timing system renovation. Thousands of WRENs are expected to be deployed across the entire CERN accelerator complex from 2027 onwards. Equipped with dedicated hardware and gateware, WREN integrates synchronisation in both TAI (International Atomic Time) and RF (accelerator Radio Frequency) timing. It can function as a TAI event transmitter and receiver, a Beam Synchronous (RF) transmitter and receiver, and is also capable of FPGA-based time-to-digital conversion and fine-delay generation. WREN is highly adaptable for various timing and trigger distribution systems. It is available in multiple form factors, including PCIe, VME, PXIe, and uTCA. All boards are based on the Zynq UltraScale+ System-on-Chip (SoC), designed using the open-source KiCad tool and licensed under the CERN Open Hardware License (OHL). The gateware and software are also open source. This paper presents the WREN hardware modules, the gateware architecture, and potential customisations for applications beyond CERN. It also shares insights from the initial pilot deployments at CERN.

The Advanced Light Source Upgrade (ALS-U) is a major upgrade project for the existing light source at Lawrence Berkeley National Laboratory. One of the key challenges of the upgrade is that the new accelerator sections cannot operate at the existing RF frequency. The injector will operate at the current RF frequency (f1 = 499.64MHz) and the new Accumulator Ring and Storage Ring will operate at a rationally related frequency (f2 = p/q * f1 = 500.39MHz). As a result, the Timing Event Generator (EVG) must be synchronous to both RF frequencies and generate separate event streams for each frequency domain. To support beam transfer from the injector (f1) to the Accumulator Ring (f2), the EVG must detect the coincidence of the two frequencies and synchronize counters to the coincidence rate.. Due to extensive need for timing channels, Event Fanout (EVF) and Event Receiver (EVR) chassis were also designed as part of this effort. This paper describes the main concepts of the Dual EVG, EVF and EVR projects, open source gateware, embedded software and EPICS IOC implementations, as well as the tests and deployment at the current ALS.

The Advanced Light Source Upgrade (ALS-U) is a major upgrade project for the existing light source at the Lawrence Berkeley National Laboratory. There is a growing interest in the community to employ ML/AI methods to use predictive analysis, optimization and error fault analysis. In order to enable those methods, a rich dataset must be available and integrated into the control system. This project aims at collecting, storing and providing methods to retrieve, initially, BPM data from the ALS-U Storage Ring, by using an additional, passive node connected to the Fast Orbit Feedback network. The data rate from just the BPMs alone would be on the order of 1Gbps (updating at a rate of 10kHz) with the requirement that the system must be able to store the data for 1 week, in a continuous manner, totaling dozens of TB of data. This paper describes a conceptual design and prototype details of the Fast Archiver. The authors are confident that the archiver can be easily extended to archiving other useful metrics of the ALS-U, like power supply setpoints and monitoring data.

This paper describes the approach to modernizing Los Alamos Neutron Science Center’s (LANSCE) Event Receiver (EVR) by replacing the Micro Research Finland (MRF) EVR with Xilinx UltraScale+ Multi-Processor System on a Chip (MPSoC). The Xilinx UltraScale+ MPSoC architecture has been chosen for this project due to its use by other teams across LANSCE and around the industry. The EVR modernization project will utilize open-source FPGA design, mrf-openevr, along with in-house implementations for interfacing. The EVR will: produce timing patterns from Event Generators (EVG) via an event link within existing time constraints, manage new and reoccurring entries into the Per Cycle Data Buffer (PCDB), and provide diagnostic tools in an easy-to-use Real Time Linux interface. The EVR modernization project is in the evaluation stage where minimum viable product criteria is being evaluated on development boards. LA-UR-25-24009

Abstract The Los Alamos Neutron Science Center (LANSCE ) has completed a significant modernization effort, migrating from the legacy RICE control system to an entirely EPICS-based infrastructure. A key enabler of this transition has been the development and deployment of modular, object-oriented Industrial I/O (IIO) architectures on National Instruments (NI) cRIO platforms. The Industrial I/O framework provides a reusable and scalable system for controlling and monitoring sensors and instruments. It is built around precompiled FPGA bitfiles accessed through NI’s C application programming interface. Where necessary, LabVIEW real-time code integrates seamlessly with EPICS IOCs. This architecture enables clear separation between control logic and hardware interfaces, supports future maintenance with minimal overhead, and accommodates both modern Linux RT cRIO and legacy VxWorks systems. The result is a flexible and resilient method for managing and improving complex control architectures across LANSCE. This contribution outlines how IIO enables hardware reuse by treating NI cards as modular components with shared logic, abstracting low-level FPGA interaction, and standardizing configurations through parameterized bitfiles and EPICs startup files. The poster and discussion focus on how this approach supports object-like behavior to improve maintainability, scalability, and cross-platform deployments of EPICS-compatible systems. LA-UR-25-24051

A proton pulse charge calculation algorithm in the Beam Power Limiting System (BPLS) at the Spallation Neutron Source (SNS) was developed and implemented in an FPGA. The algorithm calculates one-minute running average of the pulse charges and issues a fault to the Personal Protection System (PPS) and the Machine Protection System (MPS) when a limit is reached. A bit-accurate model of the algorithm was first developed and tested in Matlab® and then implemented and simulated in VHDL using Vivado® design environment. Finally, the algorithm was verified on a µTCA-based hardware platform.

The third-generation synchrotron accelerator Pohang Light Source-II (PLS-II) at Pohang Accelerator Laboratory uses a Fast Orbit Feedback (FOFB) system to maintain beam orbit stability in the storage ring. The FOFB system operates in real time to suppress orbit perturbations in both horizontal and vertical directions. Currently, the system uses VME-based Single Board Computers (SBCs) and Reflective Memory (RFM) technology, achieving a feedback repetition rate of about 1kHz. However, the aging hardware is causing difficulties in maintenance and performance upgrades. To solve this issue, a new FOFB system based on Zynq UltraScale+ FPGA high-speed digital processing technology is under development, aiming to increase the feedback rate to 10 kHz. The new design distributes twelve independent FOFB controllers throughout the storage ring to minimize latency from Beam Position Monitor (BPM) Fast Acquisition (FA) data reception to the output of control signals to the magnet power supplies. The system is being developed to work stably with the existing Fast Magnet Power Supplies at 1 kHz and also to support future high-performance supplies capable of operating at higher rates. The FPGA-based FOFB system is currently under development, with a goal of achieving a control bandwidth greater than 100 Hz and significantly improving maintainability and scalability. This paper introduces the design concept and the current development status of the new system.

A challenge that industrial particle accelerators face is the high amounts of noise in sensor readings. This noise obscures essential beam diagnostic and operational data, limiting the amount of information that is relayed to machine operators and beam instrumentation engineers. Machine learning-based techniques have shown great promise in isolating noise patterns while preserving high-fidelity signals, enabling more accurate diagnostics and performance tuning. Our work focuses on the implementation of a real-time FPGA-based noise reduction autoencoder, tested on a Xilinx ZCU104 evaluation kit with the intention of being deployed on industrial particle accelerators in the near future.