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https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA081
Title LO Board for 704.42 MHz Cavity Simulator for ESS
Authors
  • I. Rutkowski, K. Czuba, M.G. Grzegrzolka
    Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
Abstract This paper describes the requirements, architecture, and measurements results of the local oscillator (LO) board prototype. The design will provide low phase noise clock and heterodyne signals for the 704.42 MHz Cavity Simulator for the European Spallation Source. A field detection has critical influence on the simulation's performance and its quality depends on the quality of the two aforementioned signals. The clock frequency is a subharmonic of the reference frequency and choice of the frequency divider generating the clock signals is discussed. The performance of selected dividers was compared. The LO frequency must be synthesized and frequency synthesis schemes are investigated. Critical components used in the direct analog scheme are identified and their selection criteria were given.
Funding Work supported by Polish Ministry of Science and Higher Education, decision number DIR/WK/2016/03
Paper download THPHA081.PDF [0.574 MB / 4 pages]
Poster download THPHA081_POSTER.PDF [1.406 MB]
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Conference ICALEPCS2017, Barcelona, Spain
Series International Conference on Accelerator and Large Experimental Control Systems (16th)
Proceedings Link to full ICALEPCS2017 Proccedings
Session Poster Session
Date 12-Oct-17   16:45–19:00
Main Classification Hardware Technology
Keywords ion, LLRF, cavity, controls, ion-source
Publisher JACoW, Geneva, Switzerland
Editors Volker RW Schaa (GSI, Darmstadt, Germany); Isidre Costa (ALBA-CELLS, Cerdanyola del Vallès, Spain); David Fernández (ALBA-CELLS, Cerdanyola del Vallès, Spain); Óscar Matilla (ALBA-CELLS, Cerdanyola del Vallès, Spain)
ISBN 978-3-95450-193-9
Published January 2018
Copyright
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