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| WEB002 |
FPGA Mezzanine Cards for CERN's Accelerator Control System
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376 |
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- P. Alvarez, M. Cattin, J. H. Lewis, J. Serrano, T. Wlostowski
CERN, Geneva
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Field Programmable Gate Arrays (FPGAs) have become a key player in modern real time control systems. They offer determinism, simple design, high performance and versatility. A typical hardware architecture consists of an FPGA interfaced with a control bus and a variable number of digital IOs, ADCs and DACs depending on the application. Until recently the low-cost hardware paradigm has been using mezzanines containing a front end interface plus custom logic (typically an FPGA) and a local bus that interfaces the mezzanine to a carrier. As FPGAs grow in size and shrink in price, hardware reuse, testability and bus access speed could be improved if the user logic is moved to the carrier. The new FPGA Mezzanine Card (FMC) Vita 57 standard is a good example of this new paradigm. In this paper we present a standard kit of FPGA carriers and IO mezzanines for accelerator control. Carriers form factors will be VME, uTCA and PCIe. The carriers will feature White Rabbit support for accurate synchronization of distributed systems. Initial plans include IO mezzanines for 100MS/s ADCs and DACs, digital drivers and inputs, high accuracy time tag units and fine delay generators.
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Slides
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| WEB003 |
ORION Gateway Design for Feedback Controls Connectivity
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379 |
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- L. R. Doolittle, A. Ratti, C. Serrano, A. Vaccaro
LBNL, Berkeley, California
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The Optical Redundant I/O Network (ORION) is a hardware-based fast communication system for feedback controls to be implemented at NSLS-II. It controls latency by eliminating traditional computers from the communication design. Redundant communication paths give basic single-point fault tolerance. This paper describes the peripheral infrastructure for data exchange between feedback control systems and diagnostics and the communication backbone.
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Slides
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| WEB004 |
Sub-sample Time-base Resolution in a Heterogeneous Distributed Data Acquisition Environment
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382 |
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- J. A. Stillerman, W. Burke, B. Labombard
MIT/PSFC, Cambridge, Massachusetts
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Funding: This work was supported by the U. S. Department of Energy, Cooperative Grant No. DE-FC02-99ER54512
We have developed a reference timing system to verify and correct the time-bases for acquired time series data. This system allows for sub-sample time registration of data acquired from separate diagnostics using heterogeneous data acquisition hardware. The system was designed to recognize and repair several types of timing discrepancies. When used as a dedicated time-reference standard, the system relaxes the requirements for cross-diagnostic data acquisition synchronization; time-bases can be unambiguously resolved from hardware that uses asynchronous clocks and triggers. This paper will describe an automated system for generating sub-sample accurate time-bases across multiple diagnostic systems on the Alcator C-Mod experiment. We will demonstrate that we can accurately determine the times of measured phenomena in order to track point of origin and propagation around the experiment. In addition, timing errors in signals can be easily flagged and corrected. The initial installation will include fast optical systems, magnetic fluctuation measurements and plasma-sampling probes. These diagnostics are distributed around the experiment cell and have disparate digitization rates.
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| WEB005 |
Power Supply Control System of NSLS-II
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385 |
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- Y. Tian, L. R. Dalesio, G. Ganetis, W. Louie, J. Riciardelli
BNL, Upton, Long Island, New York
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A novel architecture in power supply control system at NSLS-II is discussed. The architecture provides a synchronous, deterministic and fault tolerant communication protocol for power supply control system. The architecture is designed to be able to achieve NSLS-II power supply control tasks. It also fits well into the general architecture of fast orbit feedback system and slow orbit feedback system. At NSLS-II, all the power supplies (including dipole magnet power supplies, multipole magnet power supplies and corrector magnets power supplies) will be controlled using this same architecture.
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| WEB006 |
Demonstration of an ATCA Based LLRF Control System at FLASH
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388 |
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- S. Simrock, M. K. Grecki, T. Jezynski, W. Koprek
DESY, Hamburg
- L. Butkowski, W. Jalmuzna, D. R. Makowski, A. Piotrowski
TUL-DMCS, Łódź
- K. Czuba
Warsaw University of Technology, Institute of Electronic Systems, Warsaw
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Future RF Control systems will require simultaneuous data acquisition of up to 100 fast ADC channels at sampling rates of around 100 MHz and real time signal processing within a few hundred nanoseconds. At the same time the standardization of low-level systems are common objectives for all laboratories for cost reduction, performance optimization and machine reliability. Also desirable are modularity and scalability of the design as well as compatibility with accelerator instrumentation needs including the control system. All these requirements can be fulfilled with the new telecommunication standard ATCA when adopted to the domain of instrumentation. We describe the architecture and design of an ATCA based LLRF system for the European XFEL. Initial results of the demonstration of such a system at the FLASH user facility will be presented.
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Slides
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