Yang, X. Lai, L.W. Leng, Y.B. Wan, J. Zhou, W.M. Zhou, Y.M. JACoW Publishing Geneva, Switzerland 2673-5350 978-3-95450-230-1 10.18429/JACoW-IBIC2021-WEPP32 English 443-445 cavity FPGA FEL pick-up software Contribution to a conference proceedings 2021 2021-10 https://doi.org/10.18429/JACoW-IBIC2021-WEPP32 https://jacow.org/ibic2021/papers/wepp32.pdf Digital signal processors that can handle 1 MHz bunch rate BPM signal processing is under development for SHINE. At the same time, two general purpose processor prototypes for all BPM signal sampling and processing have been developed. One uses 14bits ADC, the other uses 16bits ADC. Both processors have been completed. This paper will introduce the tests of the processors and the related performance evaluations.