Van Winkle, D. D'Ewart, J.M. Frisch, J.C. Hong, B. Legat, U. Olsen, J.J. Seward, P. Vásquez, J.A. JACoW Geneva, Switzerland 978-3-95450-177-9 10.18429/JACoW-IBIC2016-WEPG16 English 655-658 WEPG16 klystron linac timing LLRF controls Contribution to a conference proceedings 2017 2017-02 http://dx.doi.org/10.18429/JACoW-IBIC2016-WEPG16 http://jacow.org/ibic2016/papers/wepg16.pdf The low level RF control for the SLAC LINAC is being upgraded to provide improved performance and maintainability. RF control is through a high performance FPGA based DDS/DDC system built on the SLAC ATCA common platform. The klystron and modulator interlocks are being upgraded, and the interlocks are being moved into a combination of PLC logic and a fast trip system. A new solid state sub-booster amplifier will eliminate the need for the 1960s vintage high RF phase shifters and attenuators.