<xml>
  <records>
    <record>
       <contributors>
          <authors>
             <author>Hulsart, R.L.</author>
             <author>Cerniglia, P.</author>
             <author>Day, N.M.</author>
             <author>Michnoff, R.J.</author>
             <author>Sorrell, Z.</author>
          </authors>
       </contributors>
       <titles>
          <title>
             A Versatile BPM Signal Processing System Based on the Xilinx Zynq SoC
          </title>
       </titles>
		 <publisher>JACoW</publisher>
       <pub-location>Geneva, Switzerland</pub-location>
		 <isbn>978-3-95450-177-9</isbn>
		 <electronic-resource-num>10.18429/JACoW-IBIC2016-WEPG12</electronic-resource-num>
		 <language>English</language>
		 <pages>647-650</pages>
       <pages>WEPG12</pages>
       <keywords>
          <keyword>electron</keyword>
          <keyword>ion</keyword>
          <keyword>software</keyword>
          <keyword>hardware</keyword>
          <keyword>electronics</keyword>
       </keywords>
       <work-type>Contribution to a conference proceedings</work-type>
       <dates>
          <year>2017</year>
          <pub-dates>
             <date>2017-02</date>
          </pub-dates>
       </dates>
       <urls>
          <related-urls>
              <url>http://dx.doi.org/10.18429/JACoW-IBIC2016-WEPG12</url>
              <url>http://jacow.org/ibic2016/papers/wepg12.pdf</url>
          </related-urls>
       </urls>
       <abstract>
          A new BPM electronics module (V301) has been developed at BNL that uses the latest System on a Chip (SoC) technologies to provide a system with better performance and lower cost per module than before. The future of RHIC ion runs will include new RF conditions as well as a wider dynamic range in intensity. Plans for the use of electron beams, both in ion cooling applications and a future electron-ion collider, have also driven this architecture toward a highly configurable approach. The RF input section has been designed such that jumpers can be changed to allow a single board to provide ion or electron optimized analog filtering. These channels are sampled with four 14-bit 400MSPS A/D converters. The SoC's ARM processor allows a Linux OS to run directly on the module along with a controls system software interface. The FPGA is used to process samples from the ADCs and perform position calculations. A suite of peripherals including dual Ethernet ports, uSD storage, and an interface to the RHIC timing system are also included. A second revision board which includes ultra-low jitter ADC clock synthesis and distribution and improved power supplies is currently being commissioned.
       </abstract>
    </record>
  </records>
</xml>
