| Title |
Message Signalled Interrupts in Mixed-Master Control |
| Authors |
- W.W. Terpstra, M. Kreider
GSI, Darmstadt, Germany
|
| Abstract |
Timing Receivers in the FAIR control system are a complex composition of multiple bus-connected components. The bus is composed of Wishbone crossbars which connect master devices to their controlled slaves. These crossbars are in turn connected in master-slave relationships forming a DAG where source nodes are masters, interior nodes are crossbars, and terminal nodes are slaves. In current designs, masters may be found at multiple levels in the composed bus. Bus masters range from embeddedμcontrollers, to DMA controllers, to bridges from PCIe, VME, USB, or the network. In such a system, delivery of interrupts from controlled slaves to masters is non-trivial. The master may reside multiple levels up the hierarchy. In the case of network control, the master may be kilometres of fibre away. Our approach is to use message signalled interrupts (MSI). This is especially important as a particular slave may be controlled by different masters depending on the use-case. MSI allows the routing of interrupts via the same topology used in master-slave control. This paper explores the benefits, disadvantages, and challenges uncovered by our current implementation.
|
| Paper |
download THHA2O03.PDF [0.321 MB / 4 pages] |
| Slides |
download THHA2O03_TALK.PDF [0.762 MB] |
| Conference |
ICALEPCS2015, Melbourne, Australia |
| Series |
International Conference on Accelerator and Large Experimental Physics Control Systems (15th) |
| Proceedings |
Link to full ICALEPCS2015 Proccedings |
| Session |
Hardware Technology |
| Date |
22-Oct-15 09:30–10:30 |
| Main Classification |
Hardware Technology |
| Keywords |
controls, operation, FPGA, target, network |
| Publisher |
JACoW, Geneva, Switzerland |
| Editors |
Lou Corvetti (AS, Clayton, Australia); Kathleen Riches (SLSA, Clayton, Australia); Volker RW Schaa (GSI, Darmstadt, Germany) |
| ISBN |
978-3-95450-148-9 |
| Published |
December 2015 |
| Copyright |
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